Conference Agenda

Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).

 
Session Overview
Date: Tuesday, 11/Jun/2019
10:00am - 12:30pmSC1: Short course: Humidity related failure issues in electronics
Session Chair: Rajan Ambat
Humidity related failure issues in electronics
The miniaturization of electronic systems and the explosive increase in their usage has increased the humidity related reliability issues of electronics devices and components especially having metal/alloys parts exposed on the Printed Circuit Board Assembly (PCBA) surface or embedded within the multi-layer laminate. Problems are compounded by the fact that these systems are built by multi-material combinations and additional accelerating factors such as humidity absorbing and corrosion causing process related residues, bias voltage, and unpredictable user environment. Demand for miniaturised device has resulted in higher density packing with reduction in component size and closer spacing thereby increasing the electric field, while thinner metallic parts needs only nano-grams levels of metal loss for causing corrosion failures. The reduced distances on the PCBA surface also result in tiny volume of water formed from humidity to connect between terminals.
Today the knowledge on humidity related reliability issues is very limited. The short course focuses on: (i) basics of humidity interaction with PCBA surface causing corrosion failures, (ii) PCBA production process and cleanliness aspects in related to humidity related reliability issues, (iii) influence of PCBA architecture on humidity related failures, (iv) essential tips and thump rules on how to control humidity related failures, and (v) some aspects of device level design in controlling humidity entry into the device.
Auditorium 1 (S1) 
12:30pm - 1:30pmShort course lunch
Foyer 
1:30pm - 5:00pmSC2: Short course: Glasses in Semicon and Sensor applications
Session Chair: Matthias Jotz
Glasses in Semicon and Sensor applications
Glass is used in numerous Semiconductor and Sensor applications. Examples are glass carrier wafers for power ICs, which allows for Silicon wafer handling in production and back grinding. IC packaging, Micro-batteries as well as multiple Camera Imaging, Pressure Sensor & MEMS applications. In this course the current and future applications of (Thin) glasses will be highlighted as well as an overview of specialty glass manufacturing, glass processing and the properties of specialty glasses will be given. A deeper dive into structured glass substrates will also be provided.
Auditorium 1 (S1) 
6:30pm - 9:00pmCocktail Party
This is the annual Coctail Party for networking at the conference. It will be held at the Scandic Hotel Erermiatage.
Scandic Hotel Eremitage, Lyngby 
Date: Wednesday, 12/Jun/2019
8:45am - 3:00pmRegistration
Foyer 
9:00am - 9:45amOP: Opening Planary
Session Chair: Daniel Nilsen Wright
Auditorium 1 (S1) 
 

The New Advanced Packaging Era

E Jan Vardaman

TechSearch International, Inc., United States of America

The role of packaging and assembly in the electronics industry is changing. In the high performance space, new packaging solutions are being adopted to achieve the economic advantages that were previously met with silicon scaling. Many of these options include heterogeneous integration in the form of silicon interposers, fan-out on substrate, and system-in-package. In the mobile space the introduction of 5G requires the development of new packaging solutions. Product ramps are steep and cost and performance targets must be met. The automotive sector with increased electronic content provides an attractive market, but reliability requirements are tough to meet. This presentation discusses the packaging changes and some of the issues being faced.

 
9:45am - 10:10amExhibit: Exhibitor Presentations
Session Chair: Rajan Ambat
Each exhibitor at NordPac will have about 5 minutes to present their company, products and services.
Auditorium 1 (S1) 
10:10am - 11:00amCoffee Break
Coffee, snack and fruits are served in the Exhibition Hall.
Exhibition hall 
11:00am - 12:30pmW1: Improving Reliability
Session Chair: Paul Collander
Auditorium 1 (S1) 
 
11:00am - 11:30am

ALD Coatings Mitigate Tin Whiskers and Upgrade Environmental Durability of Electronic Circuit Boards

Terho Kutilainen1, Marko Pudas2, Mark A. Ashworth3, Geoffrey D. Wilcox3, Jussi Hokka4

1Poltronic Ltd., Finland; 2Picosun Oy, Finland; 3Materials Degradation Centre, Department of Materials, Loughborough University, UK; 4ESTEC, ESA, The Netherlands

Picosun is undertaking a research programme, funded by the European Space Agency, in collaboration with Oy Poltronic Ab and Loughborough University, to evaluate conformal coatings made with atomic layer deposition (ALD) as a method of mitigating the growth of tin whiskers and for corrosion protection. ALD is a mature, key enabling technology in modern IC industries, and it is also utilised for corrosion protection in various special applications. As such ALD is an interesting option for the protection of assembled electronic circuit boards and modules when extremely thin, practically massless, reworkable, transparent and inert coatings are needed, especially in specific high-end applications. ALD is also a potential method to upgrade the environmental durability of commercial off-the-shelf components and modules for more demanding applications. In addition to protection against environmental factors such as moisture and pollution, results show that the ALD coatings can significantly reduce tin whisker growth and thus offer considerable potential as a reworkable whisker mitigation strategy. The latest output of these, started in 2015 (phase 1) and 2018 (phase 2), are presented.



11:30am - 12:00pm

Enhancing Bottom Terminated Components for use in harsh environments.

Mark John Walmsley

Micross, United Kingdom

Introduction.

The next generation of electronic component functionality is being supplied in package formats which potentially present issues to manufacturers producing electronics used in harsh environments.

The expectation is all electronic components will have a high reliability however some bottom terminated components are proving problematic in some applications.

This presentation will discuss issues raised by the electronic community in using bottom terminated components in harsh environments and describe potential mitigation solutions.

Packages such as QFN, LCC and LGA present unique challenges in applications operating in environments exposed to temperature changes and vibration.

The presentation explores specifically QFN packages the process used by Micross to qualify a mitigation solution the findings of the analysis and subsequent conclusions and outcome.

A typical soldered joint from a QFN package which has suffered fatigue would eventually become open circuit as per the cross-section of a peripheral connection detailed below in figure 1.

Methodology of qualification and suitability.

The methodology has been to use off the shelf components which are then modified using a Micross process. The modified component undertakes a qualification process which includes both non-destructive and destructive analysis.

The details of the analysis have been used as an indicator of process control and suitability for the solution to be used in a harsh environment.

Testing post assembly has relied on customer feedback with some in-house temperature cycling used to support the customer findings.

Results

The results from two batches of components processed will be shared as part of the presentation. Details capture included Scanning Acoustic Microscopy (SAM) for both pre and post processing.

Scanning Electron Microscopy SEM of a section through a sample detailing intermetallic layers and solder structure, X-Ray Fluorescence (XRF) of the finished modification , Ball shear of solder on peripheral pads , 3D analysis of the finished component modification and X-Ray of the assembly detailing voiding levels in the final modified device.

The presentation will discuss the findings and provide conclusions from the body of work undertaken to qualify the Micross solution.



12:00pm - 12:30pm

Thermally Conductive and Electrically Insulating PVP/Boron Nitride Composite Films for cooling applications

Ya Liu1,3, Nan Wang2, Lilei Ye2, Amos Nkansah2, Hongbin Lu3, Johan Liu1,4

1Electronics Materials and Systems Laboratory (EMSL), Department of Microtechnology and Nanoscience (MC2), Chalmers University of Technology, Kemivägen 9, SE 412 96 Göteborg, Sweden; 2SHT Smart High Technology AB, Kemivägen 6, SE 412 58 Gothenburg, Sweden; 3State Key Laboratory of Molecular Engineering of Polymers, Department of Macromolecular Science, Collaborative Innovation Center of Polymers and Polymer Composites, Fudan University, 2005 Songhu Road, Shanghai 200433, China; 4SMIT Center, School of Mechanical Engineering and Automation, Shanghai University, No 20, Chengzhong Road, Shanghai, Box 808, 201800, China

Thermally conductive but electrically insulating materials have been extensively investigated for the purpose of thermal management of electronics. High thermal conductivity, structural stability, anti-oxidant properties, especially electric insulation performance make hexagonal boron nitride (h-BN) a promising candidate for this purpose. Theoretical studies have revealed that h-BN has a high in-plane thermal conductivity up to 400 Wm−1 K−1 at room temperature. However, it is still a big challenge to achieve high thermally conductive h-BN micron range thick film due to its fragile properties. Thus, combining the merits of polymer and the high thermal conductivity of h-BN particles is considered as a promising solution for this issue.

In this work, electrospinning was used to assist in orientating polyvinylpyrrolidone (PVP) chains and h-BN sheets. A highly h-BN loading up to 70% is able to achieve by adjusting the concentration of electrospinning solution. Besides, UV-light was used to further cross-link PVP chains to improve the water resistance of the h-BN/PVP composite film. The result shows that we can significantly improve the thermal conductivity of the composite film, thus making this approach very interesting as a candidate for the potential electronics cooling applications.

Fig. 1 (a) photograph of PVP/h-BN composite film; (b) SEM image of PVP/h-BN fiber; (c) SEM image of h-BN sheets; (d) SEM image of sintered PVP/h-BN fiber.

 
12:30pm - 1:30pmLunch and Exhibition
DTU Canteen 
1:30pm - 3:00pmW2: Additive Manufacturing
Session Chair: Dag Robert Andersson
Auditorium 1 (S1) 
 
1:30pm - 2:00pm

A novel low cost roll-to-roll compatible ultra-thin chip integration and direct metal interconnection process for flexible hybrid electronics

Nagarajan Palavesam1,2, Waltraud Hell1, Andreas Drost1, Christof Landesberger1, Christoph Kutter1, Karlheinz Bock2

1Fraunhofer EMFT, Munich, Germany; 2Technische Universität Dresden, Dresden, Germany

The emerging Internet-of-Everything (IoE) framework targets to revolutionise human-machine interaction where billions of sensors and actuators placed on almost every physical object will be tasked to communicate with each other. A substantial fraction of these devices will be placed on locations that would undergo repeated bending deformation (such as sensors for prosthetics, human body and robots) or on curved surfaces (like interior as well as exterior of automobiles, buildings and industrial equipment). Therefore, flexible sensors and actuators providing high performance at low power requirements and manufactured at low cost will be the key for successful implementation of IoE. Though massive developments achieved in printed and organic electronics have enabled them to fulfil the required flexibility and low cost for IoE applications, printed and organic electronics often fall short of the high performance and low power requirements demonstrated by silicon ICs. Therefore, silicon ICs would be the automatic choice to satisfy the demands of IoE. However, silicon ICs commercially available as standard surface mount device (SMD) components lack the bendability and conformability required for several IoE applications. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 µm are exceptionally flexible and therefore they can be integrated in flexible polymer foils to create flexible hybrid electronic (FHE) components that can be used to replace rigid SMD components. However, low cost reliable integration and interconnection of such ultra-thin bare silicon ICs is a huge bottleneck hindering the industrial high volume manufacture of such FHE components. Standard IC interconnection processes such as wire bonding may not be applied to ultra-thin bare silicon ICs as the high mechanical forces involved in the process would fracture the ICs. Therefore, we propose an innovative roll-to-roll process compatible low cost approach for direct metal interconnection of ultra-thin silicon ICs. Our process follows a face-up integration approach where bare ultra-thin silicon ICs with a thickness of 20 µm having daisy chain patterns were bonded on 50 µm thick polyimide foils with the bond pads facing up. Then, a low cost embedding polymer was coated on top of the ICs with a film applicator. After curing of the polymer in a hot plate, via holes were drilled with a laser through the polymer layer on to the IC pads. Next, interconnecting copper redistribution layer with thickness varying from 2 to 10 µm were patterned using semi-additive metallisation process comprising of sputtering, lithography and electroplating. Finally, the interconnected FHE components were precisely diced with a laser for further handling. The thickness of the fabricated flexible package with the integrated and interconnected ultra-thin IC was as thin as 100 µm. Electrical measurements conducted on the 60 fabricated samples with integrated flexible ultra-thin ICs revealed a very promising yield of 94%. The attached microscopic images present the top view of the 100 µm thin flexible package showing the integrated ultra-thin IC with the daisy chain interconnection patterns and the cross-section of a single interconnection.



2:00pm - 2:30pm

Additive Manufactured Metal Components with Integrated Optical Fiber Sensors

Dag Robert Andersson, Klas Brinkfeldt

RISE IVF, Sweden

This work aims at realising real time mesurements in industrrial processes by combining fiber optic sensors with additive manufacturing to integrate temperature and strain sensors in metal components. Additive manufacturing is used to create a network of sensors embedded inside the metal components. This approach is useful in several applications. We will present a fiber optic sensor network integrated in press hardening tools to monitor the contact between the tool and the metal sheet during forming operation The maximum operational temperatures for the tools at long term service range from 10 °C to 600 °C. Thermo mechanical simulations and experimental data will be presented that demonstrates the operation of the sensor network.



2:30pm - 3:00pm

Flexible Circuit Board Package Embedded with Multi-stack Dies

Nobuki Ueta1, Shunsuke Sato1, Koji Munakata2, Masakazu Sato1, Yoshio Nakao1, Osamu Nakao1

1Medical Electronics Department Fujikura Ltd.; 2Medical Electronics Department Fujikura Europe Ltd.

Miniaturization of electronics module is always required in various medical applications such as hearing aids and implantable devices. Many types of high density packaging technologies, such as package-on-package, bare-die stack, flex folded package and Through Si Via (TSV) technologies, have been proposed and used to fulfill the request. Among them, embedded die technology is one of the promising technologies to realize miniaturization and high density packaging. We have developed WABE(wafer and board level device embedded) technology for embedding dies into multilayer flexible printed circuit (FPC) boards. The WABE package is comprised of thin dies (85 um thickness), multi-layer polyimide, adhesive films and conductive paste. The dies are sandwiched by polyimide films having Cu circuits (FPCs). The conductive paste provides electrical connections between the layers as well as the layer and embedded die. First, each FPC layer is fabricated individually, and via holes are filled with conductive paste, and the dies are mounted on certain layers. Then, all layers undergo a one-step lamination process, and they are pressed to cure the adhesive material and conductive paste at a time. This WABE Technology has enabled multiple dies to be embedded by the one-step lamination process. Even if multiple dies are embedded, the footprint of a package can be reduced drastically by embedding multiple dies vertically in stacks. This paper describes the details of the results of fabricating a test vehicle which has six embedded dies (three-dies in two stacks side-by-side). The fabricated test vehicle had 14 copper layers with less than 0.9 mm thickness. This paper also reports the results of various reliability testing on the package. These results were obtained by electrical measurements of daisy chain patterns formed between some of the layers. The fabricated test vehicle showed high reliability based on the results of a moisture and heat test and heat-shock test. These results show that the WABE technology to embed multiple dies vertically in polyimide film is one of the most promising packaging technologies to significantly miniaturize electronic circuits such as medical electronics.

 
3:00pm - 3:50pmCoffee Break
Coffee, snack and fruits are served in the Exhibition Hall.
Exhibition hall 
3:50pm - 4:20pmIMAPS Nordic Annual Meeting
Session Chair: Daniel Nilsen Wright
Auditorium 1 (S1) 
4:10pm - 5:10pmBus to Conference dinner.
16:10 from Gentofte hotel.
16:20 from Scandic Eremitage Hotel.
16:30 from DTU.
 
5:10pm - 9:30pmConference dinner
The conference dinner will be held at Esrum Abbey & Millfarm, Klostergade 11-12, Esrum, 3230 Græsted.
Esrum Abbey & Millfarm 
9:30pm - 10:20pmBus from Conference dinner.
Departure: 21:30
Drop-off at Scandic Eremitage Hotel: 22:10
Drop-off at Gentofte Hotel: 22:20
 
Date: Thursday, 13/Jun/2019
9:00am - 10:30amT1A: Ever Increasing Density
Session Chair: Terho Kutilainen
Auditorium 1 (S1) 
 
9:00am - 9:30am

From ISHM to IMAPS, networking in microelectronics industry and academia

Paul Collander

Retired, Finland

This paper is a historic review of the R&D activities in microelectronics and packaging with examples of technologies from different years and photos from ISHM / IMAPS events 1974 - 2018. Technology development projects, activities and supporting actions are described from national and international management view, including the impact of IMAPS organizations.

Member benefits will be reported, both direct and indirect benefits, based on long term experience.

IT development in society is also reflected on the activities in IMAPS.

Some key players like Karel Kurzweil, Peter Barnwell, Nihal Sinnadurai, Hans Danielsson, Eero Järvinen and Sören Nörlyng will be portrayed (if accepting).

The competition with IEEE CPMT / EPT is brought to a controlled collaboration.



9:30am - 10:00am

Laser-lift-off (LLO) and CONDOx for wafer ultra-thinning process for 3D stacked devices, TSV, eWLB and WLCSP

Manuel Kruse

Disco-Hi-Tec Europe GmbH, Germany

Manuel Kruse

DISCO HI-TEC EUROPEGmbH

Liebigstrasse 8

D-85551 Kirchheim b. München

Tel.: +49 89 9090 3202

Fax.: +49 89 9090 3298

Email: m.kruse@discoeurope.com

Abstract

DISCO Corporation is a leading manufacturer for equipment and tools for wafer thinning and dicing.

“Bringing science to comfortable living by Kiru (Dicing), Kezuru (Grinding) and Migaku (Polishing)” is DISCO’s mission. By combining these three core technologies, DISCO provides total solutions to meet the more and more demanding requirements of the Semiconductor industry in terms of manufacturing thin dies with high die-strength and several new approaches for advanced packaging.

Wafer ultra-thinning is essential for advanced 3D packaging, at the same time challenging. The final thickness of the substrate is very small and the bumps may be higher than the substrate thickness for 2,5D interconnects. At DISCO, we deal with the extreme thinness of wafers and have developed solutions to make thinning processes as efficient as possible, to protect the product and to allow for easier handling of TSV, eWLB and WLCSP wafers.

Extreme thin grinding is a key component of 3D stacked devices interconnected by TSVs and advanced semiconductor scaling. For some products, the final thickness of the silicon is up to 10 μm or even smaller. Yet, at a certain thickness, wafers lose their rigidity and tend to warp or break easily. Temporary bonding is a countermeasure where a glass carrier is bonded temporarily to the wafer. However, the main issue is to release the wafer from the glass carrier after thinning down the silicon without wafer breakage or high tension.

A laser-supported release (Laser-Lift-Off) has been developed by DISCO which has several advantages towards other release techniques like chemical or thermal release. In the presentation, we will discuss the latest updates of Laser Lift-Off in wafer-on-wafer (WOW) technology and which benefits come with our optimized technologies.

Further, we will introduce our latest solutions for thinning eWLB or WLCSP wafers with high bumps. We will give examples how DISCO’s CONDOx technology allows for thinning wafers with final Si thickness of 25 μm and 200 μm bump height without residues, edge chipping and a further improved total thickness variation (TTV).

DISCO Hi-Tec Europe GmbH, having its facilities close to Munich airport, offers certified Dicing and Grinding Production Services, so that customers can utilize most of afore mentioned Disco technologies in production, even without investing into DISCO equipment.



10:00am - 10:30am

Through Silicon Vias in MEMS packaging, a review

Guido Sordo, Cristian Collini, Sigurd Moe, Daniel Nilsen Wright

SINTEF, Norway

Trough Silicon Via (TSV) is a key enabling technology to achieve the integration of various dies by exploiting the third dimension. This allows integration of heterogeneous chips in a single package (2.5D integration) or achieving higher integration densities of transistors (3D integration). These vertical interconnections are widely used for both IC and MEMS devices. This paper reviews TSV technology focusing to their implementation in MEMS sensors with a broad overview on the various fabrication approaches and their constraints in terms of process compatibility. A case study of an inertial MEMS sensor will then be presented.

 
9:00am - 10:30amT1B: Materials for Reliability
Session Chair: Rajan Ambat
Auditorium 2 (S9) 
 
9:00am - 9:30am

Investigation of materials for low load electrical contacts

Lise Thornfeldt Hansen, Abhijeet Yadav Yadav, Rajan Ambat, Morten S. Jellesen

Technical University of Denmark, Denmark

The more widespread use of electronics in various climatic environments requires stable, reliable and durable electrical contacts for a relatively long life span. Besides being electrically conductive the materials used for electrical contacts need to be corrosion resistant and in many cases wear resistant in order to minimize the risk of fretting and sliding wear as e.g. when replacing batteries. Traditionally contact materials have been plated with a few microns thick gold layer to ensure low electrical resistance as well as proper corrosion resistance. Gold thickness influences the corrosion of the contact as corrosion products grow through pores in the gold layer if not thick enough. The cost of gold and its low wear resistance has led to a search for alternative contact materials to be investigated.

In order to establish a proper electrical connection in a material coupling an uninterrupted passage of electrical current across the contact interface is needed. Between mating surfaces in an electrical contact the actual metal-to-metal contact is small compared to the apparent area of the two surfaces physically touching each other. The real metal-to-metal contact zone and its ability for electrical current flow depends on contact force, asperities and material type. If sliding wear occurs complex processes take place at the interface and wear debris may form and cause changes in the contact resistance.

This work describes the effects of coating combinations used for electrical contacts as nickel, tin-nickel and several gold layer thickness on stainless steel and how wear affects the electrical functionality of contact coupling. The substrate investigated is stainless steel and the counterpart in the electrical contact is nickel plated stainless steel. A novel test setup allowing for low load (below 100 g) contact situations with sliding reciprocating wear (2 mm) was used. Electrical contact resistance is measured when the mating surfaces are in static conditions after each wear cycle.

Detailed surface topography, cross sectional analysis and hardness measurements are performed on the electrical contact material couplings prior to electrical resistance measurements which are monitored online during the wear cycle. The electrical contact materials are investigated thoroughly after the wear cycle with SEM/EDS analysis together with estimation of material wear loss and investigation of wear debris particles build up in the wear track.

Results show that the effect of wear cycles has a larger effect on the electrical contact resistance for some material couplings. The effect of starting a new wear track on an unworn counterpart surface also has a larger effect on some material plating types due to differences in wear debris building up in the wear track.



9:30am - 10:00am

Low-temperature Cu-Cu thermocompression bonding for encapsulation of a MEMS mirror

Henri Vilhem Johannes Ailas, Jaakko Saarilahti, Tuomas Pensala, Jyrki Kiihamäki

VTT Technical Research Center of Finland, Finland

Copper thermocompression is a wafer-level packaging technique having many promising features. The bond between the two surfaces is formed by diffusion of atoms from one surface to another. This diffusion is inhibited by a barrier forming surface oxide, low temperature and high surface roughness. The three most common thermocompression bonding materials are Cu, Al and Au. Out of these, copper was chosen due to its low cost and high self-diffusivity. The native oxidation on copper surfaces can be completely removed with combination of ex situ acetic acid wet etch and in situ forming gas anneal.

In this study a low temperature wafer-level packaging process aimed for encapsulating MEMS mirrors was developed. The glass cap wafer used in the package has an antireflective (AR) coating that limits the maximum temperature of the bonding process to 250°C. This temperature is below the eutectic temperature of most common eutectic bonding materials, such as Au-Sn (278°C), Au-Ge (361°C) and Au-Si (370°C).

Two methods were used for fabricating the bonding structures. In the first method, a TiW adhesion layer and a 300 nm Cu seed layer were sputtered on thermally oxidized Si wafers. Next, the bond structures were fabricated by electrodeposition through a photoresist mask, after which the resist was removed. Finally, the Cu seed layer and TiW adhesion layer were wet etched. In the second method, a TiW adhesion layer and a 1000 nm Cu layer were sputtered on thermally oxidized Si wafers. Next, the bond structures were fabricated from the sputtered layer by wet etching the Cu and TiW using a photoresist mask.

Of the two fabrication methods, the later was found to produce smother bond surfaces resulting in higher bond quality. The bond strength for wafers bonded at 250°C was measured to be 44 MPa and 150 MPa for electrodeposited and sputtered structures, respectively. The dicing yield was notably higher for sputtered (99%) than electrodeposited (94%) bond structures. Effect of the process for the AR-coating was determined by exposure to the forming gas anneal and 1 h heat treatment at 250°C. No change was observed in the optical transmittance for samples with or without heat treatment. The transmittance at wavelength of 950 nm was measured to be 99.2% and 93.5% for 600 µm thick borosilicate wafers with and without AR-coating, respectively.

The study presents a successful thermocompression bonding process for sputtered Cu films at a low temperature of 200°C with high yield of 97% after dicing. The bond strength was recorded to be 75 MPa, well above the MIL-STD-883E standard (METHOD 2019.5) rejection limit of 6.08 MPa. The high dicing yield and bond strength suggest that the thermocompression bonding could be possible even at temperatures below 200°C. However, the minimum bonding temperature was not yet determined in this study.



10:00am - 10:30am

Electrochemical study on etching ability and humidity robustness of organic amines used in the solder flux systems

Feng Li, Kamila Piotrowska, Morten Stendahl Jellesen, Rajan Ambat

Centre for Electronics Corrosion, Department of Mechanical Engineering, Technical University of Denmark, Denmark

Weak organic acids (WOAs) were commercially used as flux activators, and presented as flux residue on printed circuit board assemblies (PCBAs) after soldering process. Due to the hygroscopic and ionic nature of WOAs, water layer formed on PCBAs triggers to the corrosion related failures of electronic devices. Therefore, orgainic amines were proposed as alternative materials for flux activator selection due to the redox reaction with copper oxidation layer. However, the water absorption behavior and corrosive nature of organic amines are various due to different molecular structures.

This paper investigated the etching ability and water absorption behavior of 5 selected hydroxyl group based amines after different thermal activation conditions using electrochemical methods. Etching ability of amine aqueous solution on Cu was investigated using potential dynamic polarization test. Under constant temperature of 25 ℃/40 ℃/ 60 ℃, water absorption behavior of thermal activated/non-thermal activated amines were tested on surface insulation resistance (SIR) comb pattern using electrochemical impedance spectroscopy (EIS) method with a frequency of 10 kHz in climatic chamber. The impact of humidity and temperature on thermal activated/non-thermal activated amines were investigated using DC leakage current measurement on SIR comb pattern. Thermal degradation of amines was investigated using fourier-transform infrared spectroscopy (FT-IR) and thermal gravimetric analysis (TGA) method.

This study shows two of the amines possessed better etching ability compared to commercial used WOAs but with lower degradation temperature below 240℃ and higher humidity robustness before and after thermal activation.

 
10:30am - 11:10amCoffee Break
Coffee, snack and fruits are served in the Exhibition Hall.
Exhibition hall 
11:10am - 12:40pmT2A: Pushing the Limits
Session Chair: Johan Liu
Auditorium 1 (S1) 
 
11:10am - 11:40am

Corrosion of Electronics in Oil-filled submersible pumps

Jesper Kjærnulf Konge, Annemette Riis

Grundfos A/S, Denmark

Submersible water pumps will be exposed to very harsh environments during their service life. Not only the very wet environment itself exposes a risk of deuteriation and malfunction, but also the use of advanced control electronics for the pump. The power electronics need to be cooled by the water surrounding the pump, and at the same time protected from exposure to water. In any case the electronics compartment needs to be hermetically sealed from the environment to prevent the electronics from exposure to water or humidity. To improve the cooling of the electronics within the sealed compartment, it has been chosen to fill the space with oil. The oil will also reduce the moisture content in the compartment, as it displaces the air in the compartment. These factors should not allow moisture to affect the electronics, hence the evolution of corrosion or electrochemical migration. But exactly these conditions were found in a pump returned from field conditions, which failed catastrophically. But no findings indicated a catastrophic leak between the watery environment and the electronics compartment, which indicates that very small amounts of humidity has been present in the compartment. This is on the other hand difficult to argue for, as the corrosion and electro migration was present over a very large area of the product. Another interesting aspect is that the effects of humidity was present along the vertical axis of the electronics, but normally it would be along the horizontal axis if big amounts of liquid water has been present. Furthermore, no water was found in the compartment or oil after disassembly of the pump. The talk will focus on the extensive analysis which has been performed to find the root causes of the symptoms, and to investigate the failure mechanisms which lead to the spreading of the humidity in the oil-filled compartment with no mechanical mixing of the oil. Lastly the talk will reflect upon the results of different test which has been performed to investigate the properties of the oil used for filling the compartment.



11:40am - 12:10pm

Humidity barrier properties of coatings used to protect electronics against corrosion

Ioannis Mantis, Feng Li, Vadimas Verdingovas, Rajan Ambat, Morten S. Jellesen

Center for Electronic Corrosion, Section of Materials and Surface Engineering, Department of Mechanical Engineering, Technical University of Denmark, 2800 Lyngby, Denmark

Acrylic, polyurethane, epoxy and silicone are polymer types used to protect sensitive electrical circuits from humidity ingress and other environmental factors. Despite the use of protective coatings, failures of electronics are reported due to humidity and corrosion. Failure types include increased leakage current and a reduction in surface insulation resistance (SIR) between adjacent conducting lines or electrochemical migration. Important factors for coatings humidity barrier protection are besides low water uptake and diffusion to the electronics interface also adhesion, i.e. minimizing of process-related residues remaining on the printed circuit board assembly (PCBA) surface.

This work focuses on the effect of water uptake of different types of coatings applied on a SIR pattern allowing for leakage current monitoring under various temperature and humidity exposures. The effect of flux residue contamination under the coating is also investigated by online impedance and leakage current monitoring. The deliquescence and crystallization behaviour of flux residues have been investigated under cyclic climatic conditions and will be correlated to the performance of precontaminated and coated SIR patterns with a post analysis of SIR patterns with and without flux contamination under various coating types.

The use of AC impedance technique combined with leakage current measurements at 5 V DC of SIR test substrates exposed to temperature cycling under high humidity conditions provides information on the water uptake of the coating itself as well as information on the adhesion loss between a PCBA surface and the coating during humidity exposure. The results show that the flux residue type under a conformally coated PCBA has an effect of the surface insulation resistance and leakage current levels and the various coating thickness and types strengths and weaknesses are shown.



12:10pm - 12:40pm

Scalability of Copper Interconnects down to 3um on Printed boards by Laser-assisted Subtractive method

Sarthak Acharya, Shailesh Singh Chouhan, Jerker Delsing

Luleå technical university, Sweden, Sweden

As per the updated road-map of iNEMI (upto 2017), both electronics production industries and academic research are emphasizing on identifying disruptive technologies that can contribute to denser and robust packaging. Tighter integration from transistor scale to Printed Circuit Boards (PCBs) with high density interconnects will result in miniaturization and flexibility in the end product for all application oriented services. Thus, one of the primary demands of Application Specific Integrated Circuit (ASIC) with reduced feature size is in the trend. As a result, there is a stringent condition to reduce the packaging factor of Printed Boards to accommodate greater number of ICs to support miniaturization. The present work is a contribution towards achieving Copper interconnects with feature size 3.0 micrometers (μm) which is nearly 70% lesser than the current industrial PCBs interconnects (~20 micron). In this experimental method, a commercially available photosensitive material coated FR-4 PCBs has been used. Next, reverse-mode Laser assisted writing was implemented to pattern the desired copper tracks. Then-after a well-controlled chemical etching of the activated regions were done using Sodium Hydroxide solution followed by aqueous solution of Sodium Persulfate. The key factors that make the small achieved copper track sustainable in harsh environment i.e. high temperature and pressure, are accurate etching time, optimized etchant solution and the controlled power of Laser beam used. Slight deviations in these factors will result in under etching, over-etching and poor peel strength. Other highlights of this subtractive method include its cost-efficiency, lesser production time and easy recycling. Further reliability assessment of interconnects are under progress.

 
11:10am - 12:40pmT2B: Technology Qualification
Session Chair: Heidi Lundén
Auditorium 2 (S9) 
 
11:10am - 11:40am

From the failure analysis to anamnesis and its feedback to qualification procedures

Juergen Gruber

RoodMicrotec, Germany

Electronic systems are becoming increasingly complex and the density of electrical integration is increasing as well. This has the consequence that the mutual influence of components also increases.

Failure analysis shows that this change also affects the cause of the failure. In many cases, the problem is not caused by the failed component, but the component is just the victim of another failure mechanism.

For failure analysis, this means that holistic approach must be given to system levels and not the failed component must be considered in isolation.

Similar to the medicine we can name it anamnesis. While failure analysis begins with the component, the anamnesis first focuses on the system level. All information from the process chain is collected and evaluated.

Component manufacturing, component processing, system analysis, as well as the ambient conditions in the application are to be considered. The error history must also be noted.

The presentation shows some examples of failure analyzes, which reveal the complexity of the analysis. On the basis of a diagram it is shown which ways lead to a successful analysis to finally determine the failure mechanism, which can be roughly divided into thermal or thermomechanical influences, electrical influences or environmental conditions and operational conditions.

The results obtained in failure analysis can be used to optimize qualification processes and adapt them to the application.

For the qualification of electronic components, qualification procedures are still used in most cases, which are specified in international standards such as AEC-Q, ESCC, Telcordia, Jedec, IEC. These are based on different stresses which can occur in the application and try to simulate these component loads with accelerating stress tests.

It is becoming more and more apparent that, due to the complexity of today's systems, interactions occur that are not covered in a standardized qualification process. Very often it comes to failures, which take place only with the simultaneous occurrence of several different stresses. An example is the use of QFN packages in high temperature and vibration loading applications, which leads to short circuits of adjacent solder joints.

The presentation gives hints on how to use results from failure analysis to optimize qualification processes.



11:40am - 12:10pm

The role of sensing in reliability methodologies and prognostication of failures

Dag Robert Andersson, Klas Brinkfeldt, Andreas Lövberg, Per-Erik Tegehall

RISE IVF, Sweden

Traditional reliability assessment methodologies have limitations and combined with more complex systems their accuracy is not sufficient. A new methodology is required for the reliability assessment of future electronic systems. A promising approach is to combine Physics-of-Failure based models with data-driven, AI-based methods to assess the health of the system in real time and prognosticate failures. Availability of new in-situ sensing methods and concepts such as big data handling and cloud computing makes it possible to monitor and assess the reliability of each system individually.

 
12:40pm - 1:40pmLunch and Exhibition
DTU Canteen 
1:40pm - 2:40pmT3: Corrosion Barriers
Session Chair: Daniel Nilsen Wright
Auditorium 1 (S1) 
 
1:40pm - 2:10pm

Corrosion reliability of electronic devices: Effect of contamination levels on pitch distance on PCBA

Sajjad Bahrebar, Rajan Ambat

Center for Electronic Corrosion, Section of Materials and Surface Engineering, Department of Mechanical Engineering, Technical University of Denmark 2800 Lyngby, Denmark

Corrosion reliability of electronic materials and devices is a significant issue due to many factors such as worldwide spread use as well as various demands of users for portability of electronic devices in different environments and locations; which caused an increase in the assembly design density or miniaturization on the Printed Circuit Board Assemblies (PCBAs). Various Weak Organic Acids (WOAs) as activators in typical no-clean flux systems commonly used in electronic device industries. Adipic acid (C_6 H_10 O_4) and Glutaric acid (C_5 H_8 O_4) are both WOAs, which act as activators for soldering process; moreover, they are the main ionic residues of solder flux systems on the PCBA surfaces. Adipic acid and Glutaric acid have mild and high activation, furthermore low and high solubility in water, respectively. In this study, the effect of different contamination levels for each of the two WOAs on pitch distances are estimated with using four different Surface Insolation Resistance (SIR) patterns at 300μm, 600μm, 1000μm, and 2000μm sizes. The corrosive behavior and relationships between critical factors are investigated under the maximum relative humidity of 99% with ten Direct Current (DC) voltage at a test temperature of 25°C for one day of each specimen. The results show the effects and impacts of contamination levels in the supposed 25μg/cm², 50μg/cm², 75μg/cm², and 100μg/cm² ranges of each contamination types, on different pitch distance in maximum humidity and ambient temperature. In addition, the contamination level value of each kind of contaminations assessed as a basis of failure starting on each pitch distance. Besides, display failure magnitude mean, the number of failures also time to failure of each pitch distance for investigation of corrosion reliability influenced by the leak currents diagrams.



2:10pm - 2:40pm

Implementation of flexible displays for smart textiles using processes of printed electronics

Artem Ivanov

University of Applied Sciences Landshut, Germany

The goal of the project SmartFoilDisplay is to create demonstrators of flexible displays for smart textiles that can be cost effectively manufactured in small-scale production using currently available technologies. The displays should be light emitting, capable of presenting moving texts or simple graphics and readable from distances of several meters. They should have reasonable lifetime under real environmental conditions and a reasonable price. In our previous work printed electroluminescent matrix displays were documented [1-3], here we assess additionally the use of LEDs and OLEDs as light emitting elements.

Currently a field test of printed electroluminescent matrix displays integrated in jackets is being carried out, its planned duration is from March 2019 to February 2020. Twelve volunteers are asked to wear jackets equipped with displays in their everyday life and to log the character and the duration of usage. Later similar LED-based display systems will be produced and tested under real conditions. The field test should not only reveal technical issues but also deliver information on social aspects of the intended application, e.g. on general acceptance and degree of interest to such displays in clothing for different age groups, on especially important use cases, on the limits of application etc. The results will be used to analyse, which system parameters (like mechanical flexibility, stretchability, pixel brightness, size and resolution of the matrix) are especially important for the use case. They will also serve to set the direction of further development.

In this paper the complete experimental system is described: the two types of electroluminescent displays screen printed on PET substrates, the display driver electronics with a Bluetooth Low Energy interface and the Android App for the interaction with the display. Furthermore, the paper discusses results of measurements carried out during the development phase and evaluates the performance of manufactured display systems. Reliability of different variants of the flex-to-rigid connection between the display and the driver was tested, the test results and the error codes are presented. Features and technical implementation details of the systems based on electroluminescence and on light emitting diodes were compared:

- driver topology and requirements on the components,

- requirements on the printed structures,

- power consumption and possible practical display brightness,

- mechanical flexibility and thickness of the display,

- measures to ensure the reliability of the system.

The brightness change of the manufactured printed electroluminescent displays was measured in long-time tests, evaluation of the results is presented in the paper along with the preliminary results of the field tests.

 
2:40pm - 3:00pmClosing Session
Auditorium 1 (S1) 

 
Contact and Legal Notice · Contact Address:
Privacy Statement · Conference: NordPac 2019
Conference Software - ConfTool Pro 2.6.129
© 2001 - 2019 by Dr. H. Weinreich, Hamburg, Germany