Conference Agenda

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Session Overview
SES 5.1: Data science in semiconductor manufacturing
Wednesday, 28/Jun/2017:
11:20am - 1:00pm

Session Chair: Chen-Fu Chien
Location: Aula Convegni (first floor)

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60. Data Mining for Yield Improvement of Photo Spacer Process in the Color Filter Manufacturing

Tsung-Lun Tsai, Chia-Yen Lee

National Cheng Kung Universisty, Taiwan

Manufacturing in TFT-LCD panel seeks a way for yield improvement and more efficient operating process. However, due to the complex manufacturing process of color filter, the panel manufacturer usually employs the design of experiments as well as engineering experience for process monitoring and quality control. This study aims to develop a three-stage data mining framework to identify the key variables significantly affecting the thickness of photo spacer process in color filter manufacturing. In the first stage, data preprocessing, we address the disorganized data with missing value and noise, and transform the dataset into a structured data frame. In the second stage, feature selection, due to the high-dimensional dataset with the small size of the observations, we develop a pre-filter module embedded with three selection methods to identify the statistically-significant variable. In the third stage, prediction and validation, two predictive models are built and the performance of the proposed models is evaluated. Finally, we report the selected variables and give feedback to the on-site engineers for the engineering validation in practice. In the validation loop, we may remove some factors, and then go back to the previous stage and repeat the circulate framework. An empirical study of a leading color filter manufacturer in Taiwan was conducted to validate the proposed framework. That result shows that the proposed framework greatly enhances the effectiveness and efficiency on identifying the key factors for yield improvement in color filter manufacturing and saves the labor resource for trouble-shooting.

62. Data Mining for Delamination Diagnosis in the Semiconductor Assembly Process

Shao-Yen Hung, Yung-Lun Lin, Chia-Yen Lee

National Cheng Kung University, Taiwan, Taiwan

The delamination in die-attach layer is a problem that results in defects of semiconductor products. There are several elements and parameters, which are difficultly observed, causing delamination during the assembly process. Thus, it’s critical to identify abnormal factors immediately for the real-time correction and improvement. This paper proposes a two-stage analysis framework to achieve two goals: identifying the key factors affecting delamination via variable selection and predicting the ratio of the delamination area in a die via the prediction models. In the first stage, due to the high-dimensional problem in the dataset, we apply L1 regularized regression (i.e. LASSO) and stepwise regression to extract critical variables that show significantly influence on delamination. In the second stage, we build up three models with different geometric illustrations─ backpropagation network (BPN), support vector regression (SVR) and partial least squares (PLS), to predict the delamination ratio in a die. An empirical study of a leading semiconductor assembly company in Taiwan is conducted to validate the proposed framework. The results show that some variables we finally identify are confirmed by engineer test to present potential physical meanings, and the BPN model provides better predicting accuracy. Further, we investigate the imbalance between false positive rate and false negative rate after the quality classification, and apply the gradient boosting machine (GBM) to improve the imbalance problem and give some insights for supporting practical decision.

188. Multi-Pass Lot Scheduling Algorithm for Maximizing Throughputs at Semiconductor Final Test Facilities

Sang Won Yoon, Young Min Joung, Tian He, Ravi Vancheeswaran, Cecille Abela, Herwina Richelle Andres

State University of New York at Binghamton, United States of America

This research proposes a multi-pass oriented scheduling heuristic algorithm to determine the test schedules, machine setups, and job assignments for multi-pass lots at a semiconductor final test facility with an objective of maximizing the lot throughput. The proposed algorithm dispatches a group of selected lots and all their passes at a time. The performance of the algorithm is evaluated using the subset data from industry. The results indicate that the proposed heuristic can improve the rate of weekly lot throughput by 9.46% and 7.76% on average compared to the results obtained from the single-pass oriented and the genetic algorithm, respectively.

242. Tool planning model with calibration in semiconductor equipment manufacturer

YiHsuan Yang, Chen-Yang Cheng

National Taipei University of Technology, Taiwan

This research is motivated by issues confront with a large manufacturer of semiconductor equipment. In producing semiconductor equipment, when the number of tool sent back to the supplier to be calibrated is different greatly in month. This will result in production tool shortage problem. In order to avoid the shortage problem at the time of production, the number of tools to be calibrated each month should be taken into consideration when scheduling the tool. Therefore, this research is to develop a tool planning model with tool calibration quantity balance monthly. This model balances the calibrated tool quantity every month.

294. Anomaly Detection Approaches for Semiconductor Manufacturing

Gian Antonio Susto, Matteo Terzi, Alessandro Beghi

University of Padova, Italy

Smart production monitoring is a crucial activity in advanced manufacturing for quality, control and maintenance purposes. Advanced Monitoring Systems (AMSs) aim to detect anomalies and trends; anomalies are data patterns that have different data characteristics from normal instances, while trends are tendencies of production to move in a particular direction over time.

Instruments to implement efficient AMSs are provided by Machine Learning (ML). ML approaches have proliferated in recent years Advanced Process Control (APC) solutions for Semiconductor Manufacturing, thanks to the algorithmic advancements in the field and the increased computational and storage capabilities in the IT architecture of the Fabs; ML-based approaches have been used for Virtual Metrology, Predictive Maintenance and Fault Detection applications. In this work we compare state-of-the-art ML approaches (ABOD, LOF, OnlinePCA and HOTSAX) to detect outliers and events in high-dimensional monitoring problems.

The compared anomaly detection strategies have been tested on a real industrial dataset related to a Semiconductor Manufacturing Etching process; the data available consists of 1970 wafers belonging to a set of 282 (not complete) lots, for which Optical Emission Spectrometry (OES) are available; the process in question is plasma etching, for which OES data represents a non-costly and informative source of information from a chemical point of view. The dataset also includes information on another important quantity, the Etching Rate, that is the ratio between the depth of the created trench and the time taken to perform the ‘excavation’. The Etch Rate is used in this work as a quality indicator for the produced wafers: outliers or changes seen in the Etch Rate can be considered as anomalies or changes in the production. Unfortunately the Etch Rate is costly to compute in production and in some production settings is not available for most produced wafers; this scenario underlines the importance of an AMS that is able to infer anomalous situations from different data sources, like OES data.

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