Device density in semiconductor chips continues to increase through many innovations. For example, high-NA EUV lithography enables the printing of smaller features that allow more devices in a smaller area. In addition, many innovations are taking place in the area of 3D device integration where devices are stacked on each other.
Manufacturing state-of-the-art chips with sufficient yield requires good control of many process steps during manufacturing. Overlay, for example, is a critical parameter in chip manufacturing. Overlay describes the lateral mis-alignment between 2 overlapping layers in a device. Any misalignment (=overlay error) can result in significant yield loss and overlay must therefore be controlled to the 1 nm level. These levels of control need accurate and robust overlay metrology.
Overlay is often measured on dedicated targets using optical microscopy. However, robustly achieving sub-nanometer precision requires near-perfect microscopic imaging conditions which drives the need for high-quality imaging optics with very low aberration levels. Technically this is possible, but it leads to complex and costly optical imaging systems. In order to keep metrology costs to acceptable levels there is a need for a microscopy approach that achieves the sub-nanometer precision levels in a more cost-efficient way.
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